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_________________________________________________________________________________________DS3106DK
List of Figures
Figure 1-1. DS3106DK Board Floorplan...................................................................................................................... 4
Figure 4-1. Software Main Screen ............................................................................................................................... 8
Figure 4-5. Software-Programmable DFS Window ................................................................................................... 13
Figure 4-6. Software I/O Pins Window ...................................................................................................................... 14
Figure 4-7. Software Register View Window ............................................................................................................. 15
List of Tables
Table 4-1. Mapping Between Input Clock Software Fields and DS3106 Register Fields ........................................... 9
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3106 Register Fields ............................................... 9
Table 4-4. Mapping Between T0 APLL Software Fields and DS3106 Register Fields ............................................. 10
Table 4-5. Mapping Between T4 APLL Software Fields and DS3106 Register Fields ............................................. 10
Table 4-6. Mapping Between Output Clock Software Fields and DS3106 Register Fields ...................................... 11
Table 4-7. Mapping Between DPLL Software Fields and DS3106 Register Fields .................................................. 11
Table 4-8. Mapping Between REFCLK Software Fields and DS3106 Register Fields ............................................. 11
Table 4-9. Mapping Between I/O Pins Software Fields and DS3106 Register Fields............................................... 14
Rev: 012208
3 of 32
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